In this video, I explain binary counters and how to implement them on an FPGA using Verilog.
I start with the basics by designing a 4-bit binary counter in Verilog and explaining how a counter works internally. From there, I dive into overflow behaviour — why it happens, how binary counters naturally wrap around, and why counting restarts from zero after the maximum value.
Next, I design a limit-based counter, where the counter resets to zero after reaching a specific value instead of overflowing naturally. After covering that concept, I scale the design up to a 16-bit counter.
For each design, I write a testbench and walk through the simulation waveforms, explaining proper clock generation using an unconditional always block, reset behaviour in testbenches, and how to interpret counter outputs correctly.
Once the 16-bit counter is verified in simulation, I implement it on the FPGA and connect the counter bits to 16 LEDs. At this stage, I explain why all the LEDs appear to be constantly ON instead of visibly toggling. This leads to a discussion on clock frequency, the MSB frequency of a binary counter, and human persistence of vision, which prevents us from seeing very fast transitions.
Finally, I further divide the clock to slow the counter down, allowing the binary counting pattern to become clearly visible on the LEDs.
This video is ideal for beginners learning Verilog, FPGA timing concepts, clock division, counters, and simulation practices.
In this video, you will learn:
• Binary Counter Basics: Designing a 4-bit counter and understanding overflow behaviour
• Limit-Based Counting: How to reset a counter after reaching a specific value
• Verilog Testbenches: Writing proper simulation code, generating clocks with unconditional always blocks, and handling resets
• Hardware Implementation of 16-bit counter to the FPGA
• Slowing down the clock to make binary counting visible to the human eye
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00:00 In this Video
00:30 Introduction
03:15 Verilog Design
05:30 Testbench Verification
09:25 Vivado Simulation
16:00 Common Pitfalls
17:15 Limit Based Counter
19:40 16-Bit Counter
20:40 Adding Constraints
21:20 Generated Schematic
22:40 FPGA Demonstration
23:45 Why are LEDs appearing static?
25:50 Slowed counter FPGA Demo
26:50 Conclusion